Enhanced parallel protection circuit

ABSTRACT

An enhanced parallel protection circuit is provided. A system using separate battery packs in a parallel configuration is arranged with multiple protection circuit modules (PCMs). The PCMs are configured to detect fault conditions, such as over voltage, under voltage, excess current, etc. The PCMs can be configured to control associated switches and/or other components. When a fault condition is detected by an individual PCM, the individual PCM transitions to a fault state, and the PCM triggers an output causing one or more actions, e.g., causing a device to shut down or isolate one or more components. In addition, by the use of the techniques disclosed herein, the individual PCM can generate a control signal that causes other PCMs to transition to a fault state. The individual PCM can also receive a control signal from another PCM to cause the individual PCM to transition to a fault state.

BACKGROUND

Many developments have been made to improve the way batteries are usedin mobile devices. For instance, some circuits provide safety featuresin case a battery is exposed to high levels of current. Although therehave been some improvements in recent years, there are many shortcomingsand inefficiencies when it comes to some current technologies. Forexample, some current battery protection schemes offer limited featureswhen it comes to redundancy protection. When multiple protectioncircuits are utilized, some designs do not allow the protection circuitsto communicate, and thus do not allow any type of coordination betweenprotection circuits. Such designs can lead to an inhibited ability toprotect a battery string, which is likely to lead to seriousconsequences, ranging from the unwanted discharge, overcharging, leakageor even fire.

The disclosure made herein is presented with respect to these and otherconsiderations.

SUMMARY

An enhanced parallel protection circuit is provided and describedherein. In some configurations, a system can include separate batterypacks in a parallel configuration with multiple protection circuitmodules (PCMs). The PCMs are configured to detect fault conditions, suchas over voltage, under voltage, excess current, etc. The PCMs areconfigured to detect other types of fault conditions based on atemperature of a device and/or component. The PCMs can be configured tocontrol associated switches and/or other components. When a faultcondition is detected by an individual PCM, the individual PCMtransitions to a fault state, and the PCM activates an output signalcausing one or more components to transition. An activation of theoutput signal, for example, can cause a component, such as a switch, totransition to a state that can shut down or isolate one or morecomponents. In addition, by the use of the techniques disclosed herein,the individual PCM can generate a control signal that causes other PCMsto transition to a fault state. The individual PCM can also receive acontrol signal from another PCM to cause the individual PCM totransition to a fault state. As will be described in more detail below,configurations disclosed herein mitigate occurrences where a multi-PCMdevice is operating after at least one PCM has detected a faultcondition. Configurations disclosed herein provide safeguards andredundant protection in scenarios where a fault event is detected by onePCM and not detected by another PCM in a parallel configuration.

In one illustrative example, a multi-PCM system using multiple batterypacks in a parallel configuration is arranged with sensors incommunication with each PCM configured to detect fault conditions. Whena fault condition is detected by a first PCM, the first PCM activates anoutput signal causing one or more components, e.g., a switch, totransition. In addition, the first PCM activates a control signal thatis received by other PCMs, causing the other PCMs to transition to afault state. The other PCMs each activate an output signal causingcomponents in communication with the other PCMs to transition. Theoutput signal of the first PCM remains activated while the faultcondition detected by the first PCM is present. In addition, the controlsignal of the first PCM remains activated while the fault conditiondetected by the first PCM is present.

When the fault condition detected by the first PCM is no longer present,the first PCM deactivates the control signal providing an indication toother PCMs that the fault condition detected by the first PCM is nolonger present. The first PCM also determines if the other PCMs havedetected a fault condition. The output signal of the first PCM remainsactivated if at least one PCM of the other PCMs detects a faultcondition and communicates an activated control signal to at least oneinput of the first PCM. When the control signal generated by the otherPCMs indicates that no other PCM has detected a fault condition, andwhen the fault condition detected by the first PCM is no longer present,the first PCM deactivates the output signal.

The first PCM is also configured to transition to a fault state when thefirst PCM receives an activated control signal from another PCMdetecting one or more fault conditions. When the first PCM receives anactivated control signal from another PCM, the first PCM activates anoutput signal causing one or more components, e.g., a switch, totransition. When the control signal generated by the other PCMs isdeactivated, e.g, the control signal indicates that no other PCM hasdetected a fault condition, and when the first PCM does not detect afault condition, the first PCM deactivates the output signal.

It should be appreciated that the above-described subject matter mayalso be implemented as part of an apparatus, system, or as part of anarticle of manufacture. These and various other features will beapparent from a reading of the following Detailed Description and areview of the associated drawings.

This Summary is provided to introduce a selection of concepts in asimplified form that are further described below in the DetailedDescription. This Summary is not intended to identify key features oressential features of the claimed subject matter, nor is it intendedthat this Summary be used to limit the scope of the claimed subjectmatter. Furthermore, the claimed subject matter is not limited toimplementations that solve any or all disadvantages noted in any part ofthis disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic diagram of an enhanced parallel protectioncircuit.

FIG. 2 shows a state diagram illustrating aspects of a protectioncircuit module.

FIG. 3 shows a schematic diagram of an enhanced parallel protectioncircuit where individual protection circuits include multiple outputsthat are coupled in accordance with the configurations disclosed herein.

FIG. 4 shows a schematic diagram illustrating details of componentsshown in FIG. 3.

FIG. 5 shows a schematic diagram of an enhanced parallel protectioncircuit having components for controlling paths of connectivity betweena power source node and multiple batteries.

FIG. 6 shows a schematic diagram of an enhanced parallel protectioncircuit where individual protection circuits include multiple outputsthat are coupled to components for controlling paths of connectivitybetween a power source node and multiple batteries.

FIG. 7 shows a schematic diagram illustrating details of the componentsused for controlling the connectivity between a power source node andmultiple batteries.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanied drawings, which form a part hereof, and which is shown byway of illustration, specific example configurations of which theconcepts can be practiced. These configurations are described insufficient detail to enable those skilled in the art to practice thetechniques disclosed herein, and it is to be understood that otherconfigurations can be utilized, and other changes may be made, withoutdeparting from the spirit or scope of the presented concepts. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the presented concepts is defined onlyby the appended claims. For example, some examples illustrate a systemhaving two batteries but it can be understood that the techniquesdescribed herein can be applied to systems will more than two batteriesand more than two PCMs.

Throughout the specification and claims, the following terms take themeanings explicitly associated herein, unless the context clearlydictates otherwise. The meaning of “a,” “an,” and “the” includes pluralreference, the meaning of “in” includes “in” and “on.” The term“connected” means a direct electrical connection between the itemsconnected, without any intermediate devices. The term “coupled” means adirect electrical connection between the items connected, or an indirectconnection through one or more passive or active intermediary devicesand/or components. The terms “circuit” and “component” means either asingle component or a multiplicity of components, either active and/orpassive, that are coupled to provide a desired function. The term“signal” means at least a wattage, current, voltage, or data signal. Theterms, “gate,” “drain,” and “source,” can also mean a “base,”“collector” and “emitter,” and/or equivalent parts.

An enhanced parallel protection circuit is provided and describedherein. In some configurations, a system can include separate batterypacks in a parallel configuration with multiple protection circuitmodules (PCMs). The PCMs are configured to detect fault conditions, suchas over voltage, under voltage, excess current, etc. The PCMs areconfigured to detect other types of fault conditions based on atemperature of a device and/or component. The PCMs can be configured tocontrol associated switches and/or other components. When a faultcondition is detected by an individual PCM, the individual PCMtransitions to a fault state, and the PCM activates an output signalcausing one or more components to transition. An activation of theoutput signal, for example, can cause a component, such as a switch, totransition to a state that can shut down or isolate one or morecomponents. In addition, by the use of the techniques disclosed herein,the individual PCM can generate a control signal that causes other PCMsto transition to a fault state. The individual PCM can also receive acontrol signal from another PCM to cause the individual PCM totransition to a fault state. In some configurations, an individual PCMdoes not transition from the fault state to a normal operating stateuntil all PCMs indicate they do not detect a fault condition. Asdescribed herein, configurations disclosed herein mitigate occurrenceswhere a multi-PCM device is operating after at least one PCM hasdetected a fault condition. Configurations disclosed herein providesafeguards and redundant protection in scenarios where a fault conditionis detected by one PCM and not detected by another PCM in a parallelconfiguration. Configurations disclosed herein mitigate occurrenceswhere a multi-PCM device is operating after at least one PCM has shutdown.

FIG. 1 shows a schematic diagram of a parallel protection circuit 100,also referred to herein as the “circuit 100.” As shown, the circuit 100includes a first PCM 101A and a second PCM 101B, both of which can beindividually and generically referred to herein as a “PCM 101.” Inaddition, the circuit 100 can include a first battery 102A and a secondbattery 102B, both of which can be individually and generically referredto herein as a “battery 102.” It can be appreciated that this examplecircuit 100 is provided for illustrative purposes and is not to beconstrued as limiting. Techniques, system and apparatuses disclosedherein can be applied to any suitable circuit 100 having two or morePCMs 101 and any number of batteries 102.

In some configurations, an individual PCM 101 includes one or moreinputs and at least one output. The PCMs 101 are configured totransition to a fault state when a value of a signal at the one or moreinputs meets or exceeds one or more thresholds. For example, anindividual PCM 101 can have one or more sensors 111 to detect a voltageand/or current with respect to a first input (VDD) and/or a second input(VSS). Any suitable threshold or combination of suitable thresholds canbe used with the techniques disclosed herein. For example, a thresholdfor preventing a voltage and/or current that is capable of damaging atleast one battery 102 or any other component can be used with thetechniques disclosed herein. The one or more sensors 111 can beconfigured with one or more components for detecting a temperature,level of humidity, air pressure or any other condition that can affectthe circuit 100 or other components.

To coordinate the PCMs 101 of the circuit 100, an individual PCM 101 canalso include a general-purpose input/output (referred to herein as a“GPIO” or a “control interface”). In some configurations, the GPIO ofeach PCM 101 is coupled to a common node. The GPIO can function in twomodes: (1) an input mode for detecting an activated control signal ordetecting a deactivated control signal; and (2) an output mode forgenerating an activated control signal or generating a deactivatedcontrol signal. While the GPIO is in output mode, an output controlsignal can be at a high level, e.g., greater than 2 volts, or at a lowlevel, 0 volts or less than a volt. For illustrative purposes, a controlsignal can default to a high level. “Activation” of the control signalcan include a transition of the control signal from a high level to alow level. For illustrative purposes, an “activated” control signalremains at a low level until the control signal is “deactivated.” The“deactivation” of the control signal can include a transition of thecontrol signal from a low level to a high level. For illustrativepurposes, a “deactivated” control signal remains at a high level untilthe control signal is “activated.”

In some configurations, each GPIO is configured such that, when GPIOs ofmultiple PCMs are coupled to a common node, the activation of a controlsignal generated by any single GPIO causes the control signal at thenode to be low. This can be achieved by any suitable design, one whichmay include an open drain configuration. Thus, any GPIO operating in theinput mode can detect an activated control signal generated by at leastone PCM 101, even if another PCM 101 is generating a deactivated controlsignal.

As summarized above, the circuit 100 can comprise any number of PCMs101. In such configurations, the GPIO of each PCM 101 can be coupled tothe same node to enable the coordination disclosed herein. Theseexamples are provided for illustrative purposes and is not to beconstrued as limiting, it can be appreciated that an individual PCM 101can produce any suitable voltage level for an activated or deactivatedcontrol signal. For illustrative purposes, the examples disclosed hereininclude an “activated” control signal that includes a transition from ahigh level to a low level. Alternatively, to accommodate othercomponents, an “activated” control signal can include a transition froma low level to a high level, and a “deactivated” control signal caninclude a transition from a high level to a low level.

In one illustrative example, an individual PCM 101 can have a normaloperating state and at least one fault state. A PCM 101 can beconfigured to transition from the normal operating state to a faultstate when an activated control signal is received at the GPIO. Inaddition, a PCM 101 can be configured to transition from a normaloperating state to a fault state when one or more sensors 111 of a PCM101 detects a fault condition. When a fault condition is detected by oneor more sensors 111 of a particular PCM 101, that particular PCMgenerates an activated control signal at its GPIO. The activation of thecontrol signal by at least one PCM causes all other PCMs to transitionto a fault state. Additional details regarding the GPIO and otheroperating states of a PCM 101 are described in more detail below.

When an individual PCM 101 transitions to a fault state, the PCM 101activates one or more outputs to control one or more components. In thisexample, an output of the first PCM 101A is coupled to a first node 121and an output of the second PCM 101B is coupled to a second node 122.When the first PCM 101A transitions to a fault state, the first PCM 101Aactivates the output coupled to the first node 121. Similarly, when thesecond PCM 101B transitions to a fault state, the second PCM 101Bactivates the output coupled to the second node 122.

In some configurations, when in the normal operating state, the outputof an individual PCM 101 can be at a high level, and when in a faultstate, an output can be at a low level. This example is provided forillustrative purposes and is not to be construed as limiting, it can beappreciated that an individual PCM 101 can produce any suitable voltagelevel as an output for either state. For illustrative purposes, theexamples disclosed herein include an “activated” output that includes atransition from a high level to a low level. Alternatively, toaccommodate other components, an “activated” output can include atransition from a low level to a high level, and a “deactivated” outputcan include a transition from a high level to a low level.

The circuit 100 can also include one or more components that arecontrolled by the PCMs 101. For example, the circuit 100 can include oneor more switches that control connectivity paths between two or morecomponents, a component and a ground node, a component and a powersource node, or a component and another device. In one illustrativeexample, the circuit 100 can include a first switch 103A and a secondswitch 103B (“switches 103”). Switches are used in the examples forillustrative purposes and are not to be construed as limiting. It can beappreciated that other components, e.g., controllable resistors,transistors, or op amps, can be controlled by an output of any PCM 101to accommodate other designs.

In the example of FIG. 1, the first switch 103A comprises an inputcoupled to the first node 121. The first switch 103A can also beconfigured to create a high impedance path or an open circuit for thefirst path 131 when the first switch 103A is “off.” The first switch103A can be configured to turn “off” when the output of the first PCM101A at the first node 121 is activated. The first switch 103A can beconfigured to create a low impedance path or a closed circuit for afirst path 131 when the first switch 103A is “on.” The first switch 103Acan be configured to turn “on” when the output of the first PCM 101A atthe first node 121 is deactivated. In this example, the first path 131couples an anode of the first battery 102A to a ground node 126.

The second switch 103B comprises an input coupled to the second node122. The second switch 103B can also be configured to create a highimpedance path or an open circuit for the second path 133 when thesecond switch 103B is “off.” The second switch 103B can be configured toturn “off” when the output of the second PCM 101B at the second node 123is activated. The second switch 103B can be configured to create a lowimpedance path or a closed circuit for a second path 133 when the secondswitch 103B is “on.” The second switch 103B can be configured to turn“on” when the output of the second PCM 101B at the second node 123 isdeactivated. In this example, the second path 133 couples an anode ofthe second battery 102B to the ground node 126.

In some configurations, the operating states of each PCM 101 can becontrolled by a state machine 112. FIG. 2 shows a state diagramillustrating aspects of an example set of operating states of the PCMs101. As shown in FIG. 2, a PCM can have at least five states. Generallydescribed, in State A, a PCM 101 is in a “normal operating state,” whereno fault condition is detected by one or more sensors and no activecontrol signals are received at GPIO. In State B, a PCM 101 is in an“internal protection state,” where a sensor of a PCM 101 detects a faultcondition. In the internal protection state, the output is activated andthe control signal generated by the PCM 101 is activated. In State C, aPCM 101 is in a “clear protection state,” where the sensor of the PCM101 no longer detects the fault condition. In the clear protectionstate, the control signal generated at the GPIO is deactivated, and theoutput remains activated. In State D, a PCM 101 is in an “externalprotection state,” where a PCM 101 receives an activated control signalat a GPIO. In the external protection state, the output of a PCM isactivated. In State E, a PCM 101 is in an “exit protection state,” wherethe sensor of a PCM no longer detects a fault condition, and where thePCM 101 only detects deactivated control signals received at the GPIOfrom other PCMs 101. In the exit protection state, the output of a PCMand a control signal generated at the GPIO of the PCM are bothdeactivated. These examples are for illustrative provided forillustrative purposes and are not to be construed as limiting.

In the example circuit of FIG. 1, when both PCMs 101 are in a normaloperating state, both outputs are both deactivated. In someconfigurations, a deactivated output of each PCM 101 is at a high levelthus causing the first switch 103A and the second switch 103B to be“on.” Also, in the normal operating state, the control signal generatedat the GPIO of the first PCM 101A and the control signal generated atthe GPIO of the second PCM 101B are both deactivated.

An individual PCM 101 can transition to State B, the internal protectionstate, when the individual PCM 101 detects a fault condition using oneor more sensors 111. Generally described, in State B, an individual PCM101 can activate an output signal and activate a control signal. Forexample, if a sensor 111 of the first PCM 101A detects a current above athreshold, the first PCM 101A activates the control signal at the GPIOand the output at the first node 121.

An individual PCM 101 can transition to State D, the external protectionstate, when an individual PCM 101 receives an activated control signalat the GPIO. In continuing the example above, when the first PCM 101Aactivates the control signal at the GPIO of the first PCM 101A, thesecond PCM 101B receives the activated control signal and transitions tothe external protection state. In the external protection state, thesecond PCM 101B activates the output at the second node 122.

An individual PCM 101 can transition to State C, the clear protectionstate, when an individual PCM 101 no longer detects the fault condition.In continuing the above example, the first PCM 101A can transition tothe clear protection state when the sensor(s) 111 of the first PCM 101Ano longer detect the fault condition. In the clear protection state, thefirst PCM 101A deactivates the control signal generated at the GPIO ofthe first PCM 101A. In some configurations, the output of a PCM 101 isnot deactivated in the clear protection state. Thus, in the currentexample, when the first PCM 101A is in the clear protection state, evenwhen the fault condition is no longer detected, the output of the firstPCM 101A remains activated.

An individual PCM 101 can transition to State E, the exit protectionstate, when the fault condition is no longer detected by the first PCM101A and when no other PCM 101 is generating an activated controlsignal. In continuing the above example, after the first PCM 101A hastransitioned to State C, e.g., the fault condition is no longer detectedby the first PCM 101A, the first PCM 101A determines if any other PCM101 in the circuit 100 is generating an active control signal. When itis determined that no other PCM 101 in the circuit 100 is generating anactive control signal, e.g., the control signals received by all PCMs101 at the GPIO of the first PCM 101A are deactivated, the first PCM101A transitions to the exit protection state. In the exit protectionstate, the first PCM 101A deactivates the output at the first node 121.However, in this example, if the second PCM 101B is generating an activecontrol signal, e.g., the second PCM 101B has detected a faultcondition, the first PCM 101A will not transition to the exit protectionstate.

Referring now to FIG. 3, a schematic diagram of an enhanced parallelprotection circuit 300 (“circuit 300”) having individual protectioncircuits modules with multiple outputs are shown and described below. Asshown, the circuit 300 includes a first PCM 301A and a second PCM 301B.In addition, the circuit 300 can include a first battery 102A and asecond battery 102B. It can be appreciated that this example circuit 300is provided for illustrative purposes and is not to be construed aslimiting. Techniques, systems and apparatuses disclosed herein can beapplied to any circuit having two or more PCMs 301 and any number ofbatteries 102.

In general, configurations with multiple outputs can include at leastone input, a GPIO, and a state machine 112 associated with each output.Thus, other PCM designs, such as a PCM with a third output, can includea third set of inputs (VSS and/or VDD), a third GPIO, and a third statemachine 112, configured in a manner as described above. Whenconfigurations include more than two PCMs 301, the GPIO of each PCM 301is coupled to the GPIO of the first PCM 301A and the GPIO of the secondPCM 301B.

As shown in FIG. 3, the first PCM 301A comprises one or more inputs (VDDand VSS), a first output coupled to a first node 321, a second outputcoupled to a second node 322. The first PCM 301A is configured totransition to a first fault state and activate the first output coupledto the first node 321 when one or more values of at least one signal atthe one or more inputs (VDD and/or VSS) of the first PCM 301A meet orexceed a first set of criteria. For example, a signal could exceed afirst set of criteria if a current or voltage exceeds a threshold in afirst direction. In addition, the first PCM 301A is configured totransition to a second fault state and activate the second outputcoupled to the second node 322 when the one or more values of the atleast one signal at the one or more inputs of the first PCM 301A meet orexceed a second set of criteria. For example, a signal could exceed asecond set of criteria if a current or voltage exceeds a threshold in asecond direction.

The second PCM 301B comprises one or more inputs (VDD and VSS), a firstoutput coupled to a fourth node 324, and a second output coupled to athird node 323. The second PCM 301B is configured to transition to afirst fault state and activate the output coupled to the third node 323when one or more values of at least one signal at the one or more inputs(VDD and/or VSS) of the second PCM 301B meet or exceed the first set ofcriteria. The second PCM 301B is configured to transition to the secondfault state and activate the output coupled to the fourth node 324 whenthe one or more values of the at least one signal at the one or moreinputs of the second PCM meet or exceed the second set of criteria. Assummarized above, any suitable set of criteria can be used for eitherfault state, including criteria that is needed to protect a component ofthe circuit 300 or any device or component connected to the circuit 300.In one illustrative example, the first output and the second output canrespectively referred to as a first charge pump output (DSG) and asecond charge pump output(CHG).

The first PCM 301A also comprises a first GPIO and a second GPIO. Thesecond PCM 301B also comprises a first GPIO and a second GPIO. The firstGPIO of the first PCM 301A is coupled to the first GPIO of the secondPCM 301B. The second GPIO of the first PCM 301A is coupled to the secondGPIO of the second PCM 301B. For illustrative purposes, since someconfigurations include a state machine 112, or other suitablecontroller, for each output the individual PCMs 301 can each comprise afirst state engine 112A and a second state engine 112B. In this example,the first state engine 112A is associated with the first output, and thesecond state engine 112B is associated with the second output. Thus, theindividual PCMs 301 can have two independent engines, each operating ina manner described above with reference to FIG. 2.

When the first PCM 301A detects a first fault condition, e.g., when oneor more values of at least one signal at the one or more inputs of thefirst PCM 301A meet or exceed the first set of criteria, the first PCM301A transitions to the first fault state. More specifically, the firststate engine 112A of the first PCM 301A transitions to the internalprotection state based on the first set of criteria. When the firststate engine 112A is in the internal protection state, the first PCM301A activates the first output coupled to the first node 321, andgenerates an active control signal at the first GPIO of the first PCM301A. In response to receiving the active control signal generated atthe first GPIO of the first PCM 301A, the first state engine 112A of thesecond PCM 301B transitions to the external fault state, thereby causingthe second PCM 301B to activate the first output coupled to the fourthnode 324.

When the first PCM 301A detects a second fault condition, e.g., when oneor more values of at least one signal at the one or more inputs of thefirst PCM 301A meet or exceed the second set of criteria, the first PCM301A transitions to the second fault state. More specifically, thesecond state engine 112B of the first PCM 301A transitions to theinternal protection state based on the second set of criteria. When thesecond state engine 112B is in the internal protection state, the firstPCM 301A activates the second output coupled to the second node 322, andgenerates an active control signal at the second GPIO of the first PCM301A. In response to receiving the active control signal generated atthe second GPIO of the first PCM 301A, the second state machine 112B ofthe second PCM 301B transitions to the external fault state, therebycausing the second PCM 301B activate the second output coupled to thethird node 323.

When the second PCM 301B detects a first fault condition, e.g., when oneor more values of at least one signal at the one or more inputs of thesecond PCM 301B meet or exceed the first set of criteria, the second PCM301B transitions to the first fault state. More specifically, the firststate engine 112A of the second PCM 301B transitions to the internalprotection state based on the first set of criteria. When the firststate engine 112A is in the internal protection state, the second PCM301B activates the first output coupled to the fourth node 324, andgenerates an active control signal at the first GPIO of the second PCM301B. In response to receiving the active control signal generated atthe first GPIO of the second PCM 301B, the first state engine 112A ofthe first PCM 301A transitions to the external fault state, therebycausing the first PCM 301A to activate the first output coupled to thefirst node 321.

When the second PCM 301B detects a second fault condition, e.g., whenone or more values of at least one signal at the one or more inputs ofthe second PCM 301B meet or exceed the second set of criteria, thesecond PCM 301B transitions to the second fault state. Morespecifically, the second state engine 112B of the second PCM 301Btransitions to the internal protection state based on the second set ofcriteria. When the second state engine 112B is in the internalprotection state, the second PCM 301B activates the second outputcoupled to the third node 323, and generates an active control signal atthe second GPIO of the second PCM 301B. In response to receiving theactive control signal generated at the second GPIO of the second PCM301B, the second state engine 112B of the first PCM 301A transitions tothe external fault state, thereby causing the first PCM 301A to activatethe second output coupled to the second node 322.

In another illustrative example, when the first PCM 301A and the secondPCM 301B both detect a first fault condition, e.g., when one or morevalues of at least one signal at the one or more inputs of the first PCM301A and the second PCM 301B meet or exceed the first set of criteria,the first PCM 301A and the second PCM 301B transition to the first faultstate. More specifically, the first state engine 112A of the first PCM301A transitions to the internal protection state based on the first setof criteria. In addition, the first state engine 112A of the second PCM301B transitions to the internal protection state based on the first setof criteria.

When the first state engine 112A of the first PCM 301A is in theinternal protection state, the first PCM 301A activates the first outputcoupled to the first node 321, and generates an active control signal atthe first GPIO of the first PCM 301A. When the first state engine 112Aof the second PCM 301B is in the internal protection state, the secondPCM 301B activates the first output coupled to the second node 322, andgenerates an active control signal at the first GPIO of the second PCM301B.

In the current example, when the first PCM 301A no longer detects thefirst fault condition and the second PCM 301B still detects the firstfault condition, the first PCM 301A deactivates the control signal atthe first GPIO of the first PCM 301A, however, the output signals at thefirst output coupled to the second node 321 and the first output coupledto the second node 322 remain activated since the second PCM 301B stilldetects the first fault condition. When the first PCM 301A and thesecond PCM 301B both no longer detect the first fault condition, theoutput signal at the first output coupled to the second node 321 and theoutput signal at the first output coupled to the second node 322 aredeactivated.

A similar scenario applies to the circuit 300 when a second faultcondition is detected by both PCMs 301. When both PCMs 301 detect asecond fault condition, the second output for both PCMs 301 areactivated and the control signal generated at the second GPIO for bothPCMs 301 are activated. The outputs for both PCMs 301 are deactivatedwhen both PCMs 301 no longer detect the second fault condition. It canalso be appreciated that both PCMs 301 can detect both a first faultcondition and a second fault condition. In such a scenario, all controlsignals and all four outputs can be activated. Each control signal andeach output can be deactivated based on the techniques disclosed herein.

In some configurations, an individual PCM 301 can activate all outputsand all control signals when the first fault condition or the secondfault condition is detected. For example, the first PCM 301A canactivate the first output coupled to the first node 321 and activate thesecond output coupled to the second node 322 in response to one or morevalues of at least one signal at the one or more inputs (VDD and/or VSS)of the first PCM 301A meeting or exceeding the first set of criteria. Insuch a configuration, the first PCM 301A can also activate the firstcontrol signal at the first GPIO and second GPIO of the first PCM 301Ain response to one or more values of at least one signal at the one ormore inputs (VDD and/or VSS) of the first PCM 301A meeting or exceedingthe first set of criteria.

The first PCM 301A can also be configured to activate the first outputcoupled to the first node 321, activate the second output coupled to thesecond node 322, activate the first control signal at the first GPIO ofthe first PCM 301A, and activate the second control signal at the secondGPIO of the first PCM 301 in response to one or more values of at leastone signal at the one or more inputs (VDD and/or VSS) of the first PCM301A meeting or exceeding the second set of criteria. The second PCM301B, and other PCMs arranged in a parallel configuration, can beconfigured in the same manner, e.g., configured to activate all outputsand activate all control signals in response to the detection of eitherthe first fault condition or the second fault condition. With such anarrangement, the circuit 300 can activate all outputs when any type offault condition is detected, and all outputs can remain activated untilall fault conditions are no longer detected.

The aspects of the state diagram of FIG. 2 can be utilized by each statemachine 112 of each PCM 301. Thus, in some configurations, an activatedoutput of a PCM 301 can remain activated until all PCMs 301 haveindicated that no other like fault conditions are detected. Thus, inexpanding the examples above, if the first PCM 301A and the second PCM301B both detect a first fault condition, the first PCM 301A isconfigured to maintain an active output at first output until the secondPCM 301B indicates, via a control signal at the first GPIO, that thesecond PCM 301B no longer detects the first fault condition. Inaddition, the second PCM 301B is configured to maintain an active outputat first output until the first PCM 301A indicates, via the controlsignal, that the first PCM 301A no longer detects the first faultcondition. When both the first PCM 301A and the second PCM 301B nolonger detect the presence of the first fault condition, first PCM 301Aand the second PCM 301B can both deactivate the associated outputs,e.g., the first output of the first PCM 301A and first output of thesecond PCM 301B.

Similarly, if the first PCM 301A and the second PCM 301B both detect asecond fault condition, the first PCM 301A is configured to maintain anactive output until all PCMs 301 have indicated that no other like faultconditions are detected. If the first PCM 301A and the second PCM 301Bboth detect a second fault condition, the first PCM 301A is configuredto maintain an active output at second output until the second PCM 301Bindicates, via a control signal at the second GPIO, that the second PCM301B no longer detects the second fault condition. In addition, thesecond PCM 301B is configured to maintain an active output at secondoutput until the first PCM 301A indicates, via the control signal, thatthe first PCM 301A no longer detects the second fault condition. Whenboth the first PCM 301A and the second PCM 301B no longer detect thepresence of the second fault condition, first PCM 301A and the secondPCM 301B can both deactivate the associated outputs, e.g., the secondoutput of the first PCM 301A and second output of the second PCM 301B.

Referring now to FIG. 4, aspects of the switches (303 of FIG. 3) areshown and described below. In one illustrative example, the circuit 300comprises a first transistor 403A, second transistor 403B, thirdtransistor 403C, fourth transistor 403D, first diode 402E, second diode402F, third diode 402G, and a fourth diode 402H.

In this example, a gate of the first transistor 403A is coupled to thefirst node 321 and the source of the first transistor 403A is coupled tothe anode of the first battery 102A. The drain of the first transistor403A is coupled to the drain of the second transistor 403B. The cathodeof the first diode 402E is coupled to the drain of the first transistor403A and the drain of the second transistor 403B. The anode of the firstdiode 402E is coupled to the source of the first transistor 403A and theanode of the first battery 102A. The gate of the second transistor 403Bis coupled to the second node 322, and the source of the secondtransistor 403B is coupled to the ground node 126. The cathode of thesecond diode 402F is coupled to the drain of the first transistor 403Aand the drain of the second transistor 403B. The anode of the seconddiode 402F is coupled to the source of the second transistor 403B andthe ground node 126.

Also shown in FIG. 4, the gate of the third transistor 403C is coupledto the third node 323, and the drain of the third transistor 403C iscoupled to the drain of the fourth transistor 403D. The source of thethird transistor 403C is coupled to the ground node 126. The anode ofthe third diode 402G is coupled to the ground node 126 and the source ofthe third transistor 403C. The cathode of the third diode 402G iscoupled to the drain of the third transistor 403C and the drain of thefourth transistor 403D.

In addition, in this example, the gate of the fourth transistor 403D iscoupled to the fourth node 324. The source of the fourth transistor 403Dis coupled to the anode of the second battery 102B. The anode of thefourth diode 402H is coupled to the source of the fourth transistor 403Dand the anode of the second battery 102B. The cathode of the fourthdiode 402H is coupled to the drain of the third transistor 403C and thedrain of the fourth transistor 403D. It can be appreciated that othercomponents and/or arrangements can be used to achieve the techniquesdescribed herein as these examples are provided for illustrativepurposes.

The techniques disclosed herein enable a single PCM to control aresistance level within multiple paths, such as the paths 331-334 ofFIG. 3 or the paths 451-452 of FIG. 4. In addition to controlling alevel of resistance, a single PCM can also control the direction ofcurrent within multiple paths. In the example shown in FIG. 4, when thefirst PCM 301A and the second PCM 301B are in an operating state,current is free to flow in both directions in the two paths 451 and 452.When the first PCM 301A and/or the second PCM 301B transition to thefirst fault state, the current in two different paths 451 and 452 can becontrolled to flow in a first direction. In addition, when the first PCM301A and/or the second PCM 301B transition to the second fault state,the current in two different paths 451 and 452 can be controlled to flowin a second direction. In addition, with the first PCM 301A and/or thesecond PCM 301B transition to both the first fault state and the secondfault state, the two different paths 451 and 452 can transition to ahigh level of resistance or an open circuit. It can be appreciated thatresistance levels in other paths, such as a path between the fifth node430 and the sixth node 431, a path between the sixth node 431 and theground node 126, a path between the ground node 126 and the seventh node432, and a path between the seventh node 432 and the eighth node 433,can be controlled by the techniques disclosed herein.

It can be appreciated that techniques disclosed herein can control thedirection of current and/or a level of resistance for any pathconnecting or more nodes of a circuit. The examples are provided forillustrative purposes and are not to be construed as limiting. Althoughthe aforementioned examples illustrate paths that couple a battery to aground note, it can be appreciated that the paths having controlledlevels and/or directions of resistance can couple components of adevice, couple components to a ground node, couple components to a powersource, or couple components to other devices. For illustrativepurposes, FIG. 5, FIG. 6, and FIG. 7 illustrate other configurationswhere the techniques disclosed herein control multiple paths between apower source node (VBATT) and the cathode of multiple batteries.

FIG. 5 shows a schematic diagram of an enhanced parallel protectioncircuit 500 having switches controlling paths of connectivity between apower source node 121 and two batteries. Some components of FIG. 5 areconfigured in a manner similar to the circuit 100 shown in FIG. 1.However, in the example shown in FIG. 5, the first switch 103A isconfigured to control the connection between the cathode of the firstbattery 102A to the power source node 120 (“VDD”). In addition, thesecond switch 103B is configured to control the connection between thecathode of the second battery 102B to the power source node 120. Thepower source node 120 can be coupled to an external power source, e.g.,a charger, and/or a load, e.g., a motherboard of a device.

FIG. 6 shows a schematic diagram of another enhanced parallel protectioncircuit 600 having switches configured to control the connection betweena power source node 101 and two batteries. Some components of FIG. 6 areconfigured in a manner similar to the circuit 300 shown in FIG. 3.However, in the example shown in FIG. 6, the first switch 103A isconfigured to control the connection between the cathode of the firstbattery 102A to the power source node 120. In addition, the fourthswitch 103D is configured to control the connection between the cathodeof the second battery 102B to the power source node 120.

FIG. 7 shows a schematic diagram illustrating details of the componentsfor coupling the output of the individual protection circuits andswitches for controlling paths of resistance between a power source nodeand two batteries. Some components of FIG. 7 are configured in a mannersimilar to the circuit 300 shown in FIG. 4. However, in the exampleshown in FIG. 7, the source of the first transistor 403A is coupled tothe cathode of the first battery 102A. In addition, the anode of thefirst diode 402E is coupled to the source of the first transistor 403Aand the cathode of the first battery 102A. The gate of the secondtransistor 403B is coupled to the sixth node 326 and a source of thesecond transistor 403B is coupled to the power source node 120. Theanode of the second diode 402F is coupled to the source of the secondtransistor 403B and the power source node 120. The anode of thebatteries 102 are coupled to the ground node 126.

Also shown in FIG. 7, the source of the third transistor 403C is coupledto the power source node 120. The anode of the third diode 402G iscoupled to the power source node 120 and the source of the thirdtransistor 403C. In addition, in this example, the source of the fourthtransistor 403D is coupled to the cathode of the second battery 102B.The anode of the eighth diode 402H is coupled to the source of thefourth transistor 403D and the cathode of the second battery 102B.

It should be understood that the operations of the methods disclosedherein are not necessarily presented in any particular order and thatperformance of some or all of the operations in an alternative order(s)is possible and is contemplated. The operations have been presented inthe demonstrated order for ease of description and illustration.Operations may be added, omitted, and/or performed simultaneously,without departing from the scope of the appended claims. It also shouldbe understood that the illustrated methods can be ended at any time andneed not be performed in its entirety.

The above specification, examples and data provide a completedescription of the manufacture and use of the composition of theinvention. Since many embodiments of the invention can be made withoutdeparting from the spirit and scope of the invention, the inventionresides in the claims hereinafter appended.

What is claimed is:
 1. An apparatus, comprising: a first protectioncircuit module comprising one or more inputs, a control interface, andan output coupled to a first node, wherein the first protection circuitmodule is configured to activate the output coupled to the first node,activate a control signal at the control interface, and transition to aninternal protection state when a value of a signal at the one or moreinputs of the first protection circuit module meets or exceeds one ormore thresholds; and a second protection circuit module comprising oneor more inputs, a control interface, and an output coupled to a secondnode, wherein the second protection circuit module is configured toactivate the output coupled to the second node, activate the controlsignal at the control interface, and transition to the internalprotection state when a value of a signal at the one or more inputs ofthe second protection circuit module meets or exceeds one or morethresholds, wherein the control interface of the first protectioncircuit module is coupled to the control interface of the secondprotection circuit module, wherein the first protection circuit moduleis configured to activate the output coupled to the first node andtransition to an external protection state when the second protectioncircuit module activates the control signal, and wherein the secondprotection circuit module is configured to activate the output coupledto the second node and transition to the external protection state whenthe first protection circuit module activates the control signal.
 2. Theapparatus of claim 1, wherein the first protection circuit module isconfigured to transition to a clear protection state when the signal atthe one or more inputs of the first protection circuit module no longermeets or exceeds one or more thresholds, in the clear protection state,the output of the first protection circuit module remains active and thecontrol signal at the control interface of the first protection circuitmodule is deactivated.
 3. The apparatus of claim 1, wherein the firstprotection circuit module is configured to transition to an exitprotection state when the signal at the one or more inputs of the firstprotection circuit module no longer meets or exceeds one or morethresholds and when the first protection circuit module is receiving adeactivated control signal from the second protection circuit module, inthe exit protection state the output of the first protection circuitmodule is deactivated and the control signal at the control interface ofthe first protection circuit module is deactivated.
 4. The apparatus ofclaim 1, wherein the second protection circuit module is configured totransition to a clear protection state when the signal at the one ormore inputs of the second protection circuit module no longer meets orexceeds one or more thresholds, in the clear protection state, theoutput of the second protection circuit module remains active and thecontrol signal at the control interface of the second protection circuitmodule is deactivated.
 5. The apparatus of claim 1, wherein the secondprotection circuit module is configured to transition to an exitprotection state when the signal at the one or more inputs of the secondprotection circuit module no longer meets or exceeds one or morethresholds and when the second protection circuit module is receiving adeactivated control signal from the first protection circuit module, inthe exit protection state, the output of the second protection circuitmodule is deactivated and the control signal at the control interface ofthe second protection circuit module is deactivated.
 6. The apparatus ofclaim 1, further comprising: a first switch comprising an input coupledto the first node, wherein the first switch creates a low impedance pathfor a first path when the first switch is on, and wherein the firstswitch creates a high impedance path or an open circuit for the firstpath when the first switch is off, wherein the first switch isconfigured to be off when the output of the first protection circuit isactivated; and a second switch comprising an input coupled to the secondnode, wherein the second switch creates a low impedance path for asecond path when the second switch is on, and wherein the second switchcreates a high impedance path or an open circuit for the second pathwhen the second switch is off, wherein the second switch is configuredto be off when the output of the second protection circuit is activated.7. The apparatus of claim 6, wherein the first switch comprises atransistor, wherein the input of the first switch is a gate of thetransistor and the first path passes through a source of the transistorand a drain of the transistor.
 8. The apparatus of claim 6, where in thetransistor is a field-effect transistor or a metal oxide semiconductorfield-effect transistor.
 9. The apparatus of claim 1, wherein the secondswitch comprises a transistor, wherein the input of the second switch isa gate of the transistor and the second path passes through a source ofthe transistor and a drain of the transistor.
 10. The apparatus of claim9, where in the transistor is a field-effect transistor or a metal oxidesemiconductor field-effect transistor.
 11. The apparatus of claim 1,wherein the one or more inputs of the first protection circuit modulecomprise a first input coupled to a cathode of a first battery and asecond input coupled to an anode of the first battery, and wherein theone or more inputs of the second protection circuit module comprise afirst input coupled to a cathode of a second battery and a second inputcoupled to an anode of the second battery, wherein the first pathcouples the anode of the first battery to a ground node, and wherein thesecond path couples the anode of the second battery to the ground node.12. The apparatus of claim 1, wherein the one or more inputs of thefirst protection circuit module comprise a first input coupled to acathode of a first battery and a second input coupled to an anode of thefirst battery, and wherein the one or more inputs of the secondprotection circuit module comprise a first input coupled to a cathode ofa second battery and a second input coupled to an anode of the secondbattery, wherein the first path couples the cathode of the first batteryto a power source node, and wherein the second path couples the cathodeof the second battery and the power source node.
 13. An apparatus,comprising: a first protection circuit module comprising one or moreinputs, a first control interface, a second control interface, an outputcoupled to a first node, an output coupled to a second node, wherein thefirst protection circuit module is configured to activate the outputcoupled to the first node, activate a control signal at the firstcontrol interface, and transition to a first protection state when oneor more values of at least one signal at the one or more inputs of thefirst protection circuit module meets a first set of criteria, andwherein the first protection circuit module is configured to activatethe output coupled to the second node, activate a control signal at thesecond control interface, and transition to a second protection statewhen the one or more values of the at least one signal at the one ormore inputs of the first protection circuit module meets a second set ofcriteria; and a second protection circuit module comprising one or moreinputs, a first control interface, a second control interface, an outputcoupled to a third node, an output coupled to a fourth node, wherein thesecond protection circuit module is configured to activate the outputcoupled to the third node, activate the control signal at the firstcontrol interface, and transition to a first protection state when oneor more values of at least one signal at the one or more inputs of thesecond protection circuit module meets the first set of criteria, andwherein the second protection circuit module is configured to activatethe output coupled to the fourth node, activate a control signal at thesecond control interface, and transition to the second protection statewhen the one or more values of the at least one signal at the one ormore inputs of the second protection circuit module meets the second setof criteria, wherein the first control interface of the first protectioncircuit module is coupled to the first control interface of the secondprotection circuit module, wherein the second control interface of thefirst protection circuit module is coupled to the second controlinterface of the second protection circuit module, wherein the firstprotection circuit module is configured to activate the output coupledto the first node and transition to a first external protection statewhen the second protection circuit module activates the control signalat the first control interface, wherein the first protection circuitmodule is configured to activate the output coupled to the second nodeand transition to a second external protection state when the secondprotection circuit module activates the control signal at the secondcontrol interface, wherein the second protection circuit module isconfigured to activate the output coupled to the fourth node andtransition to a first external protection state when the firstprotection circuit module activates the control signal at the firstcontrol interface, and wherein the second protection circuit module isconfigured to activate the output coupled to the third node andtransition to a second external protection state when the firstprotection circuit module activates the control signal at the secondcontrol interface.
 14. The apparatus of claim 13, wherein the firstprotection circuit module is configured to transition to a first clearprotection state when the values of at least one signal at the one ormore inputs of the first protection circuit module no longer meet thefirst set of criteria, in the first clear protection state, the outputcoupled to the first node remains active and the control signal at thefirst control interface of the first protection circuit module isdeactivated.
 15. The apparatus of claim 13, wherein the first protectioncircuit module is configured to transition to a second clear protectionstate when the values of at least one signal at the one or more inputsof the first protection circuit module no longer meet the second set ofcriteria, in the second clear protection state, the output coupled tothe second node remains active and the control signal at the secondcontrol interface of the first protection circuit module is deactivated.16. The apparatus of claim 13, wherein the second protection circuitmodule is configured to transition to a first clear protection statewhen the values of at least one signal at the one or more inputs of thesecond protection circuit module no longer meet the first set ofcriteria, in the first clear protection state, the output coupled to thefourth node remains active and the control signal at the first controlinterface of the second protection circuit module is deactivated. 17.The apparatus of claim 13, wherein the second protection circuit moduleis configured to transition to a second clear protection state when thevalues of at least one signal at the one or more inputs of the secondprotection circuit module no longer meet the second set of criteria, inthe second clear protection state, the output coupled to the third noderemains active and the control signal at the second control interface ofthe second protection circuit module is deactivated.
 18. The apparatusof claim 13, wherein the first protection circuit module is configuredto transition to a first exit protection state when the values of atleast one signal at the one or more inputs of the first protectioncircuit module no longer meet the first set of criteria and when thefirst protection circuit module is receiving a deactivated controlsignal from the first control interface of the second protection circuitmodule, in the first exit protection state, the output coupled to thefirst node is deactivated and the control signal at the first controlinterface of the first protection circuit module is deactivated.
 19. Theapparatus of claim 13, wherein the first protection circuit module isconfigured to transition to a second exit protection state when thevalues of at least one signal at the one or more inputs of the firstprotection circuit module no longer meet the second set of criteria andwhen the first protection circuit module is receiving a deactivatedcontrol signal from the second control interface of the secondprotection circuit module, in the first exit protection state, theoutput coupled to the second node is deactivated and the control signalat the second control interface of the first protection circuit moduleis deactivated.
 20. The apparatus of claim 13, wherein the secondprotection circuit module is configured to transition to a first exitprotection state when the values of at least one signal at the one ormore inputs of the second protection circuit module no longer meet thefirst set of criteria and when the second protection circuit module isreceiving a deactivated control signal from the first control interfaceof the first protection circuit module, in the first exit protectionstate, the output coupled to the fourth node is deactivated and thecontrol signal at the first control interface of the second protectioncircuit module is deactivated.
 21. The apparatus of claim 13, whereinthe second protection circuit module is configured to transition to asecond exit protection state when the values of at least one signal atthe one or more inputs of the second protection circuit module no longermeet the second set of criteria and when the second protection circuitmodule is receiving a deactivated control signal from the second controlinterface of the first protection circuit module, in the first exitprotection state, the output coupled to the third node is deactivatedand the control signal at the second control interface of the secondprotection circuit module is deactivated.
 22. The apparatus of claim 13,further comprising: a first switch comprising an input coupled to thefirst node, wherein the first switch creates a low impedance path for afirst path when the first switch is on, and wherein the first switchcreates a high impedance path or an open circuit for the first path whenthe first switch is off, wherein the first switch is configured to beoff when the output coupled to the first node is activated; a secondswitch comprising an input coupled to the second node, wherein thesecond switch creates a low impedance path for a second path when thesecond switch is on, and wherein the second switch creates a highimpedance path or an open circuit for the second path when the secondswitch is off, wherein the second switch is configured to be off whenthe output coupled to the second node is activated; a third switchcomprising an input coupled to the third node, wherein the third switchcreates a low impedance path for a third path when the third switch ison, and wherein the third switch creates a high impedance path or anopen circuit for the third path when the third switch is off, whereinthe third switch is configured to be off when the output coupled to thethird node is activated; and a fourth switch comprising an input coupledto the fourth node, wherein the fourth switch creates a low impedancepath for a fourth path when the fourth switch is on, and wherein thefourth switch creates a high impedance path or an open circuit for thefourth path when the fourth switch is off, wherein the fourth switch isconfigured to be off when the output coupled to the fourth node isactivated.
 23. A method for controlling a first switch and a secondswitch, the first switch associated with a first protection circuitmodule, the second switch associated with a second protection circuitmodule, the method comprising: receiving a signal at an input of thefirst protection circuit module; generating an activated output signalat an output of the first protection circuit module in response to thesignal reaching or exceeding one or more thresholds; generating a firstactivated control signal at an interface the first protection circuitmodule in response to the signal reaching or exceeding one or morethresholds; receiving, at an interface of the second protection circuitmodule, the first activated control signal; generating a secondactivated output signal at an output of the second protection circuitmodule in response to receiving the first activated control signal atthe interface of the second protection circuit module; causing a highimpedance path in the first switch in response to receiving the firstactivated output signal at an input of the first switch; and causing ahigh impedance path in the second switch in response to receiving thesecond activated output signal at an input of the second switch.
 24. Themethod of claim 23, wherein the method further comprises: determining,at the first protection circuit module, that the signal no longerreaches or exceeds the one or more thresholds; generating a deactivatedcontrol signal at the interface the first protection circuit module inresponse to determining that the signal no longer reaches or exceeds theone or more thresholds; generating a deactivated output signal at theoutput of the second protection circuit module in response to receivingthe deactivated control signal at the interface of the second protectioncircuit module; and causing a low impedance path in the second switch inresponse to receiving the deactivated output signal at the input of thesecond switch.
 25. The method of claim 23, wherein the method furthercomprises: determining, at the first protection circuit module, that thesignal no longer reaches or exceeds the one or more thresholds;determining, at the first protection circuit module, that the secondprotection circuit module is generating a deactivated control signal;generating a second deactivated output signal at the output of the firstprotection circuit module in response to determining that the signal nolonger reaches or exceeds the one or more thresholds and that the secondprotection circuit module is generating a deactivated control signal;and causing a low impedance path in the first switch in response toreceiving the second deactivated output signal at the input of the firstswitch.
 26. The method of claim 23, further comprising: receiving asecond signal at an input of the second protection circuit module;generating a second activated control signal at an interface the secondprotection circuit module in response to the second signal reaching orexceeding at least one of the one or more thresholds; receiving, at theinterface of the first protection circuit module, the second activatedcontrol signal; determining, at the first protection circuit module,that the signal no longer reaches or exceeds the one or more thresholds;determining, at the first protection circuit module, that the secondprotection circuit module is generating the second activated controlsignal; and maintaining the activated output signal at the output of thefirst protection circuit module in response to determining that thesecond protection circuit module is generating the second activatedcontrol signal.
 27. The method of claim 26, wherein the activated outputsignal generated at the output of the first protection circuit module ismaintained until the second protection circuit module stops generatingthe second activated control signal at the interface of the secondprotection circuit module.
 28. The method of claim 23, wherein the oneor more thresholds is based on a current, a voltage, or a temperaturedetected by a sensor of the first protection circuit module.